Sr Principal Design Engineer

<p><strong style="background-color: rgb(255, 255, 255); color: rgb(71, 77, 106);">At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.</strong></p><p><strong>Job Title:&nbsp;</strong>Sr Principal Design Engineer</p><p><strong>Location:&nbsp;</strong>Noida</p><p>Electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.</p><p><br></p><p><strong><u>The Cadence Advantage</u></strong></p><ul><li>The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.</li><li>Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.</li><li>The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success</li><li>Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests</li><li>You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day.</li></ul><p><br></p><p><span style="background-color: rgb(255, 255, 255); color: rgb(71, 77, 106);">The role requires the management of a Memory Controller DV group focusing on MDV verification including Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship of junior engineers. The role requires the ability to work with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions. The role will require customer interactions including pre and post-sales activities, DV methodology review and customer support.</span></p><p><br></p><p><br></p>